1. Field of the Invention
The present invention generally relates to manufacturing, burning-in, testing, and mounting of semiconductor chips having integrated circuits. More particularly, the present invention relates to wafer-scale manufacturing, burning-in, testing, and mounting of semiconductor chip, or die, packages.
2. Background of the Invention
Typically, when manufacturing a dynamic random access memory device, for example, the manufacturing process includes constructing a semiconductor wafer of a preselected diameter which contains a plurality of individual dies. Currently, the diameter of a typically sized semiconductor wafer will frequently range from approximately 100 mm to approximately 300 mm, but wafers can be sized to have diameters which are smaller or larger than the typical diameterical range. The individual dies are singulated, or severed, from the wafer and are individually placed in packages, including but not limited to, small outline j-lead packages (SOJ), tape automated thin small outline packages (TSOP), chip scale packages (CSP), or any other of a wide variety of chip packages known within the art. After incorporating the individual dies in respective die, or chip, packages, the individual chip packages are often taken through a preburn-in test, a burn-in test which is usually conducted at elevated temperatures and voltages, and low and high speed final tests. Those chips which successfully complete each of the tests are ultimately installed upon the next higher assembly such as a circuit board, flexible substrate, or some other structure to provide a memory device, for example, and which will ultimately be incorporated in an electronic component, or product.
However, with a constant demand on the semiconductor chip industry for providing an ever increasing number of transistors on a single semiconductor chip, to increase memory capacity and/or speed for example, the industry must continuously find ways to overcome problems and inefficiencies encountered in the manufacturing, burning-in, testing, and mounting of chips on the next higher level of assembly so as to remain competitive in the market place. To illustrate, more and more transistors, or devices, are being provided within a given semiconductor die, or chip, and are becoming by necessity larger in size to accommodate the increasing number of transistors, which can range upward of a hundred million (100xc3x97106) individual transistors on a single chip. Thus, it is desirable, if not required, that the final chip package be made as small as possible to counter the physically larger dies contained therein.
One of the technical problems encountered by the industry in such ultra large scale integration (ULSI) technology is how to control, and preferably reduce, the costs associated with burning-in, testing, and then mounting dies on the next higher assembly such as on circuit boards or various substrates to be used in a given end product.
Another problem encountered in manufacturing larger sized dies designed to accommodate an ever increasing number of transistors, or devices, is contending with the stray inductance and parasitic capacitance associated with bondwires extending between the input and output bond pads located on the active surface of the die and bond pads or lead frames of the package that are in turn placed in electrical communication with various circuits on the next level of assembly. For example, a typical bond pad, or contact pad, may have a self-inductance of approximately 3-10 nanohenries (nH) and a typical bond pad, or contact pad, may have a stray capacitance of 0.2 picofarads (pF). Such unwanted, relatively large self-inductances and stray capacitances can become very troublesome upon chip frequencies approaching and exceeding 1 gigahertz.
A further problem encountered when manufacturing chips accommodating a large number of transistors is being able to quickly and reliably test and burn the chips at either a wafer level, or at a packaged chip level, without damaging the bond pads located on the active surface of the chip, or in the alternative, without damaging an electrical lead or an electrical contact that is accessible from the exterior of the chip package.
Other manufacturing and testing difficulties arise from the need to constantly update expensive test equipment as each new generation of chip packages are designed and introduced to the market. This is because such test equipment will often utilize elongated probes or cantilevered probes that resiliently extend from a structure referred to as a probe head, or probe card, in a preselected pattern to make electrical contact with a respective die bond pad either directly, or by temporarily contacting an externally accessible lead, pin, or contact if the die has already been packaged, so that burn-in and testing can be conducted.
A wafer level burn-in system is disclosed in U.S. Pat. No. 5,866,535 issued to Budnaitis which includes a semiconductor wafer being placed in a burn-in apparatus so that bond pads on the active surface of the wafer faces upwardly. The system further includes a laminated contact sheet which is positioned on top of the active surface of the wafer and a temporary, compliant, selectively conductive Z-axis member which is positioned on top of the laminated contact sheet, and a movable base unit is positioned above the stacked components of the system. The base unit is then biased downward to electrically couple the base unit, the Z-axis member, the laminated contact sheet, and the bond pads of the wafer so that burn-in and testing of the wafer can be conducted. Upon burning-in and testing of the wafer, the wafer, as well as the various components, are removed from the test apparatus and disassociated from each other so that the wafer can be forwarded for further processing.
U.S. Pat. No. 6,005,401 issued to Nakata et al. discloses a semiconductor wafer burn-in and test apparatus including a retainer board for holding a semiconductor wafer which in turn is brought into contact with a probe sheet having probe terminals corresponding to terminals on the semiconductor wafer so that burn-in and testing can be conducted on the chips or integrated circuits present on the wafer. An elastic member compensates for any unevenness that may exist with respect to the probe terminals of the probe sheet upon contacting the wafer with the probe sheet.
U.S. Pat. No. 5,959,462 issued to Lum discloses a test structure for burn-in testing of a semiconductor wafer in which the test structure incorporates a backing support wafer in which a plurality of segmented individual test integrated circuits have been attached to the backing support wafer. Conductive bumps of the attached integrated circuits which are attached to the support wafer are brought into electrical contact with integrated circuits on the product wafer so that burn-in testing can be conducted. After burn-in and testing of the product wafer, the test structure, incorporating the backing support wafer and the attached integrated circuits, is removed from electrical contact with the product wafer and the product wafer is then forwarded for further processing. The test structure of Lum is quite elaborate in that yet another silicon wafer mold upon which a thin film signal distribution layer containing various electrical signal routing circuits, optional electrical interconnects and contacts as needed between the layers of thin film signal distribution layer is used in the construction of the test structure for stabilizing the test integrated circuits as they are being attached to the backing support wafer.
U.S. Pat. No. 6,004,867 issued to Kim et al. discloses a chip package assembled at the wafer level which incorporates a silicon substrate attached to the active surface of the wafer which contains a plurality of input/output pads thereon. The substrate includes a top surface and a bottom surface. The bottom surface of the substrate is provided with a plurality of circuit traces configured to terminate at preselected positions on the bottom surface which correspond to the locations of the input/output pads on the active surface of the wafer. The circuit traces are constructed so as to be in electrical communication with a plurality of terminal pads positioned on the top surface of the substrate which may be positioned independently of the input/output pads of the active surface of the wafer. The terminal pads, formed on the top portions of the circuit traces, are provided with metallic bumps which in turn, ultimately electrically and mechanically bond to a circuit board for example. Kim et al. further discloses a method of manufacturing the chip package disclosed therein and includes the steps of providing a wafer, attaching a substrate to form a substrate-wafer-composite, lapping the substrate, forming a plurality of metallic bumps, and cutting the substrate-wafer-composite. Additional steps are set forth wherein the wafer is polished, a barrier metal layer is disposed upon the electrically conductive traces to improve the bonding of the bottom ends of the traces to the input/output pads of the active surface of the wafer, as well as lapping the top surface of the substrate to expose the terminal pads thereof and lapping of the opposite surface of the active surface of the wafer which has been attached to the bottom surface of the substrate.
Interestingly in the manufacturing method disclosed in the Kim et al. patent, the active surface of the semiconductor wafer is lapped to prepare it for attachment to the bottom surface of the substrate, then the top surface of the substrate is subsequently back-lapped after the bottom surface of the substrate has been attached to the active surface of the semiconductor wafer. Additionally, the substrate must undergo some further processing steps after being attached to the active surface of the wafer in order to expose the terminal pads on the top surface of the substrate so that solder balls can be then be disposed on the terminal pads which, in turn, will serve to electrically and mechanically attach the terminal pads to, for example, a circuit board using conventional solder attachment techniques. Thus, it appears that were one to manufacture the chip-size package disclosed in Kim et al., particular care must be taken in preparing the active surface of the wafer to be attached to the upper surface of the substrate to ensure that the active surface of the wafer is very level or flat so as to properly mate against the upper surface of the substrate which also must be very level. This is because the upper ends of the circuit traces that are to be directly attached to respective input/output pads are shown as being flush with the upper surface of the substrate. Therefore, in order for the circuit traces to properly contact the input/output pads of the active surface of the wafer, which are also flush, the levelness, or flatness, of the adjoining services of the substrate and wafer must be properly polished or lapped so that there will be no unwanted surface irregularities that could interfere with the surfaces being properly and fully attached to each other.
U.S. Pat. No. 6,032,356 to Eldridge et al. discloses a technique for providing and mounting a plurality of resilient contact structures directly upon terminals, or pads, located on the active surface of semiconductor dies while still in wafer form. The resilient contact structures can then be brought into temporary contact with corresponding contact pads located on a probe card for burn-in and testing of the yet to be singulated dies. Upon the unsingulated dies having been burned-in and tested, the wafer is forwarded on for further processing including singulation of the dies with the resilient contact structures being available for permanently connecting the dies to higher level circuits, such as a circuit board. The resilient contact structures as disclosed in Eldridge are configurable in a number of shapes and are taught as generally having a gold filament coated with a flexible nickel alloy to obtain the resilient nature of the contact structures. However, spring-like contact structures generally require that a certain amount of force be used to ensure a secure contact during burn-in and testing. When considering the number of resilient contact structures required for use when burning-in and testing ULSI wafers, the cumulative forces required for urging the large number of resilient contact structures to contact a test card, or probe, could become quite significant.
Therefore, it can be appreciated that the art continues to seek ways to produce semiconductor chips, including chips incorporating ULSI technology, in a more efficient, cost-effective manner and in which chips can easily be burned-in and tested, on a wafer-level, by readily available burn-in and test apparatus. Furthermore, the industry continues to seek to produce chips that may be packaged within chip-scale packages that are readily mounted and incorporated within the next level of assembly, such as in, but not limited to, multi-chip memory modules, rigid substrates, flexible substrates including tapes, or directly onto a printed circuit board. Yet further, the industry continues to seek to produce chip-scale packages which can be mounted with connective bonds which have extremely low, or negligible stray inductance and very low parasitic capacitance, especially as the frequency of operation of modem chips approaches and surpasses 1 gigahertz.
The present invention comprises a semiconductor device wafer being mounted on a support wafer to provide a wafer-on-wafer package which can be burned-in and tested prior to singulation of the chip-scale semiconductor die, or device, packages constructed in accordance with the present invention. Upon the wafer-on-wafer package being successfully burned-in and tested, the individual semiconductor packages contained within the wafer-on-wafer package may be singulated from the wafer-on-wafer package on an individual basis, or in groups, and directly mounted onto the next level of assembly such as upon a multi-chip memory module, a printed circuit board, a rigid substrate, or a flexible substrate including tape-like structures, for example. The present invention is particularly suitable for, but not limited to, producing chip-scale packages from semiconductor device wafers incorporating ultra large scale integration (ULSI) technology.
In accordance with the present invention, a device wafer made of a preselected material such as silicon, or other suitable semiconductor material, having integrated circuits on an active surface of the wafer is made available. Preferably the device wafer will have at least one, and preferably a plurality of, unsingulated semiconductor chips, or dice, with each unsingulated chip having a plurality of input/output bond pads on the active surface thereof. In addition to the active surface having integrated circuits thereon, the device wafer will usually have a nonactive, or back surface.
Preferably the support wafer, which is to be bonded to the device wafer, is a rejected semiconductor device wafer from the front-end of a device wafer production line and therefore significantly reduces the costs associated with producing semiconductor wafers by reclaiming what would otherwise be considered scrap material generated by the production line. Thus, the support wafer will ideally be made of the same semiconductor material as the device wafer and will have an identical coefficient of thermal expansion thus eliminating the potential for any thermally induced problems arising from the device wafer and the support wafer expanding and contracting at different rates when subjected to temperature differentials.
The top, or die connect, surface of the support wafer is provided with a plurality of chip, or die bond pad, connection elements, preferably comprising electrically conductive globules such as metallic or nonmetallic solder balls or bumps which are positioned to correspond and be bonded, attached, or otherwise connected to the plurality of bond pads located on the active surface of the device wafer. The die bond pad connections, or elements, of the support wafer are in electrical communication with respective traces which lead to vias, or feed-throughs, which extend through the cross-section of the support wafer to the bottom surface of the support wafer, also referred to as the test connection/mounting sites, or elements, of the support wafer. The vias, or feed-throughs, are arranged in a preselected pattern to preferably correspond with the plurality of test connection/mounting sites, or elements, located on the bottom surface of the support wafer which are arranged in a preselected pattern. The preselected pattern, or grid, of the test connection/mounting sites will usually be of a different, more widely spaced pattern than the pattern of bond pads located on the active surface of each die contained within the device wafer. That is, the test connection/mounting sites, or elements, will likely have a greater individual surface area and pitch, or spacing, between adjacent elements than the die bond pads located on the dies of the device wafer. The vias of the support wafer are partially or fully filled with a preselected conductive material, such as a tin and lead based solder which is flowable at elevated temperatures. The solder preferably forms a first meniscus, or globule, extending to the circuit trace associated with the via on the top surface of the support wafer. The conductive material, or flowable solder, disposed within the via also preferably extends to and slightly beyond the bottom surface of the support wafer so as to terminate in a second meniscus, or globule, such as a solder ball or bump, suitable for being contacted by a test probe and then ultimately to serve as a mounting element that can be bonded so as to provide a mechanically and electrically attachment point to a contact pad, a mounting pad, or other electrically conductive surface located on a printed circuit board, memory module board, or other electronic component or substrate in which the chip-scale die package is to be attached. Additionally or alternatively, conductive paths may be provided in the vias in accordance with the teachings of a copending U.S. patent application filed Aug. 17, 1998, having Ser. No. 09/118,346, incorporated by reference herein, and assigned to the assignee of the present invention.
Upon the support wafer being prepared as described, the active surface of the device wafer and the top surface of the support wafer are aligned with each other and are then joined by using bump or solder ball joint connections, such as controlled collapse chip connections (C4), between the bond pads on the active surface of the device wafer and the corresponding, or complementary, die pad connection elements such as solder balls provided on the die connect surface of the support wafer. Upon the device wafer and the support wafer being bonded or joined to provide a plurality of permanent electrical and mechanical connections between each of the die bond pads and respectively associated die pad connections, the wafer-on-wafer package can then be placed in a burn-in and test apparatus wherein test probes are brought into contact with test connection/mounting sites, or elements, which preferably comprise a plurality of electrically conductive solder balls, located on the bottom surface of the support wafer and which are in electrical communication with respectively associated vias, which in turn are in electrical communication with respectively associated traces, which are, in turn, in electrical communication with die bond pad connect elements, such as solder balls, which have been attached to respective die bond pads arranged in a preselected pattern on at least some, if not every active surface of each unsingulated semiconductor die.
After the wafer-on-wafer package has been burned-in and tested by a suitable wafer burn-in and testing apparatus, the individual dies of the wafer-on-wafer package can then be singulated as needed for subsequent mounting on the next level of assembly. Because, the test connection/mounting elements, globules, or solder balls are already in place on the bottom surface of the now singulated chip package, which comprises a portion of the support wafer having test connection/mounting elements thereon, the singulated chip, or chips, are ready to be mounted to the next level of assembly with little or no preparation. The test connection/mounting elements, which preferably are menisci formed by the conductive filling material, or solder, previously disposed in the vias, or feed-throughs, to form globules, such solderballs or bumps, are bonded to mounting pads, or other suitable surfaces, correspondingly positioned and arranged to accommodate the test connection/mounting elements. Solder ball connection techniques, such as those known in the art as controlled collapse chip connection (C4) techniques, are particularly suitable for bonding the test connection/mounting elements to suitable bonding sites located on a chip accommodating a substrate such as a mounting pad on a printed circuit board, a memory module board, or any other suitable substrate whether it be rigid or flexible.
These and additional features and benefits of the present invention are further described and illustrated in the following detailed description of the invention and the present drawings.